| Control Law Accelerator (CLA) OverviewThe control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLAenables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasksfrees up the main CPU to perform other system and communication functions concurently. The following isa list of major features of the CLA.•Clocked at the same rate as the main CPU (SYSCLKOUT).•An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.–Complete bus architecture:•Program address bus and program data bus•Data address bus, data read bus, and data write bus–Independent eight-stage pipeline.–12-bit program counter (MPC)–Four 32-bit result registers (MR0–MR3)–Two 16-bit auxillary registers (MAR0, MAR1)–Status register (MSTF)•Instruction set includes:–IEEE single-precision (32-bit) floating-point math operations–Floating-point math with parallel load or store–Floating-point multiply with parallel add or subtract–1/X and 1/sqrt(X) estimation |
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